The 'LS138, SN54S138, and SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs.
This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. 3 Enable Inputs to Simplify Cascading and/or Data Reception.
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